entity mux2 is
  port ( d0 : in  std_logic; -- résultat quand x vaut '0'
         d1 : in  std_logic; -- résultat quand x vaut '1'
         x  : in  std_logic;
         r  : out std_logic );
end mux2;

architecture arch of mux2 is
begin
  r <= (x and d1) or (not x and d0);
end arch;

entity majorite is
  port ( x : in  std_logic;
         y : in  std_logic;
         z : in  std_logic;
         m : out std_logic );
end majorite;

architecture arch1 of majorite is
  signal xy : std_logic;
  signal yz : std_logic;
  signal zx : std_logic;
begin
  xy <= x and y;
  yz <= y and z;
  zx <= z and x;
  m  <= xy or yz or zx;
end arch1;

architecture arch2 of majorite is
  component mux2 is
    port ( d0 : in  std_logic;
           d1 : in  std_logic;
           x  : in  std_logic;
           r  : out std_logic );
  end mux2;

  signal x00 : std_logic;
  signal x10 : std_logic;
  signal x01 : std_logic;
  signal x11 : std_logic;
  signal xy0 : std_logic;
  signal xy1 : std_logic;
begin
  mux_x00 : mux2 port map ( d0 => '0', d1 => '0', x => x, r => x00 );
  mux_x10 : mux2 port map ( d0 => '0', d1 => '1', x => x, r => x10 );
  mux_x01 : mux2 port map ( d0 => '0', d1 => '1', x => x, r => x01 );
  mux_x11 : mux2 port map ( d0 => '1', d1 => '1', x => x, r => x11 );

  mux_xy0 : mux2 port map ( d0 => x00, d1 => x10, x => y, r => xy0 );
  mux_xy1 : mux2 port map ( d0 => x01, d1 => x11, x => y, r => xy1 );

  mux_xyz : mux2 port map ( d0 => xy0, d1 => xy1, x => z, r => m );
end arch2;